Conventionally, in cases where access to a RAM needs to be controlled according to two asynchronously inputted access clocks, it is common to adopt a dual port RAM as a memory device. A dual port RAM denotes a RAM having two input/output interfaces (typically one for writes and one for reads) with respect to the storage portion within the memory device.
As one conventional technology related to the present invention, there is disclosed and proposed a dual port RAM circuit in which a single-port RAM portion is accessed on a time-division basis. In this dual port RAM, read and write control signals from two control devices are each formed into a single-clock-period-wide control signal synchronous with an internal clock and, when two control signals each from one of the two control devices happen to be synchronized to have the same timing, one of them is delayed by one clock period (see Patent Document 1 listed below).
As another conventional technology related to the present invention, there is disclosed and proposed a system control device that copes with clock asynchronism within the device. In this system control device, a clock for a firmware control portion is integrated into a clock for a main signal control portion by a clock frequency arbitration portion, and, according to a timing signal from a timing signal generation portion, access to a data storage portion by the main signal control portion and the firmware control portion is controlled on a time-division basis so as not to contend (see Patent Document 2 listed below).
Patent Document 1: JP-A-H06-161870
Patent Document 2: JP-A-2000-341255